In recent years, as the performance and function of semiconductor integrated circuit devices improve, the number of inputs/outputs to/from a semiconductor integrated circuit device is increasing. Accordingly, many more I/O cells and bonding pads are being arranged around the core region of a semiconductor integrated circuit device. Namely, to decrease the area of such semiconductor integrated circuit device, it is important to decrease the area of a pad region including these I/O cells and bonding pads.
For example, Patent Literature (PTL) 1 discloses reducing the unnecessary space in an I/O region, to provide a semiconductor integrated circuit device requiring a smaller area. According to PTL 1, I/O circuit portions and electrostatic discharge (ESD) protection element portions included in the I/O region are arranged in the length direction (cross direction) of a side of the core region.
In addition, PTL 2 discloses a technique for improving EMS of an I/O circuit portion, without increasing a layout area.    [PTL 1]    Japanese Patent Kokai Publication No. JP2007-096216A (FIG. 2)    [PTL 2]    Japanese Patent Kokai Publication No. JP2004-165246A